Summary:This is the schematic diagram of DC motor speed controller circuit. The circuit applies two oscillators/timers which are connected as a Pulse Width Modulator (PWM). The timer chip which applied in this circuit will be an nmos dual timer/osc
This is the schematic diagram of DC motor speed controller circuit. The circuit applies two oscillators/timers which are connected as a Pulse Width Modulator (PWM). The timer chip which applied in this circuit will be an nmos dual timer/oscillator NE556. This timer IC has two 555 timers in a single 14-pin IC package.
The time period for the high output is specified by
And, the low output by TLOW = 0.69R4C2 seconds. The 2nd 555 (IC1:A) is set up for Pulse Width Modulation. It will be build in monostable mode. It is triggered using the continuous pulse train from the first 555 timer. Nevertheless, by also applying a DC voltage to pin 3, the comparator reference levels are going to be modified from their nominal levels of one-third & two-thirds of the supply voltage. This has the effect of modulating the pulse width as the control voltage varies. The control voltage is supplied via transistor Q1, which is configured as an emitter-follower. This means that the emitter output voltage follows the base input voltage (less 0.6 volt base-emitter drop). This configuration gives us a low output impedance voltage source with which to drive the control input of the timer. This makes the control voltage less susceptible to the loading effect of the timer control input.
The output from the timer is a continuous stream of pulses whose width is controlled by the voltage level used on the control voltage input. This modulated output drives a MOSFET, Q2, that is applied to switch the voltage to the DC motor.
R1 = 560R
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